Production Data
WM8768
BCLK
(Output)
tDL
LRCLK
(Output)
DIN1/2/3/4
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRCLK propagation delay
from BCLK falling edge
tDL
0
10
ns
ns
ns
DIN1/2/3/4 setup time to
BCLK rising edge
tDST
tDHT
10
10
DIN1/2/3/4 hold time from
BCLK rising edge
Table 2 Digital Audio Data Timing – Master Mode
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
WM8768
DAC
DSP/
DECODER
LRCLK
DIN1/2/3/4
4
Figure 4 Audio Interface – Slave Mode
PD Rev 4.1 March 2005
9
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