WM8768
Production Data
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 DAC Master Clock Timing Requirements
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tMCLKH
tMCLKL
tMCLKY
11
11
ns
ns
ns
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
28
40:60
2
1000
60:40
10
Power-saving mode activated
Normal mode resumed
After MCLK stopped
After MCLK re-started
Us
0.5
1
MCLK
cycle
Table 1 Master Clock Timing Requirements
Note:
If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with
internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be
accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically
powered up, but a write to the volume update register bit is required to restore the correct volume settings.
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
DSP/
DECODER
WM8768
DAC
LRCLK
DIN1/2/3/4
4
Figure 2 Audio Interface - Master Mode
PD Rev 4.1 March 2005
8
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
