WM8766
Production Data
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS
0000010
BIT
LABEL
DEFAULT
DESCRIPTION
8:5
PL[3:0]
1001
PL[3:0]
Left
Right
Output
Output
DAC Control
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Mute
Left
Mute
Mute
Mute
Mute
Left
Right
(L+R)/2
Mute
Left
Left
Right
(L+R)/2
Mute
Left
Left
Left
Right
Right
Right
Right
(L+R)/2
(L+R)/2
(L+R)/2
(L+R)/2
Right
(L+R)/2
Mute
Left
Right
(L+R)/2
DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits:
REGISTER ADDRESS
0000011
BIT
LABEL
FMT
DEFAULT
DESCRIPTION
Interface Format Select:
00 : Right justified mode
01: Left justified mode
10: I2S mode
1:0
00
Interface Control
[1:0]
11: DSP modes A or B
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCLK. If this
bit is set high, the expected polarity of LRCLK will be the opposite of that shown in Figure 13, Figure
14 and Figure 15. Note that if this feature is used as a means of swapping the left and right
channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is
used to select between modes A and B.
REGISTER ADDRESS
0000011
BIT
LABEL
DEFAULT
DESCRIPTION
In left/right/I2S Modes:
2
LRP
0
Interface Control
LRCLK Polarity (normal)
0 : Normal LRCLK polarity
1: Inverted LRCLK polarity
In DSP Mode:
0 : DSP mode A
1: DSP mode B
By default, LRCLK and DIN1/2/3 are sampled on the rising edge of BCLK and should ideally change
on the falling edge. Data sources that change LRCLK and DIN1/2/3 on the rising edge of BCLK can
PD Rev 4.1 July 2005
20
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
