WM8766
Preliminary Technical Data
MPU INTERFACE TIMING
tCSL
tCSH
ML/I2S
tSCY
tCSS
tSCS
tSCH
tSCL
MC/IWL
MD/DM
LSB
tDSU
tDHO
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
MC/IWL rising edge to ML/I2S rising edge
MC/IWL pulse cycle time
SYMBOL
tSCS
MIN
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
tSCY
ns
MC/IWL pulse width low
tSCL
ns
MC/IWL pulse width high
tSCH
ns
MD/DM to MC/IWL set-up time
MC/IWL to MD/DM hold time
ML/I2S pulse width low
tDSU
ns
tDHO
tCSL
ns
ns
ML/I2S pulse width high
tCSH
ns
ML/I2S rising to MC/IWL rising
tCSS
ns
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
PTD Rev 2.3 February 2004
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
