WM8750JL
Production Data
PIN DESCRIPTION
PIN NO
1
NAME
MCLK
TYPE
Digital Input
DESCRIPTION
Master Clock
Supply
Digital Core Supply
Digital Buffer (I/O) Supply
2
DCVDD
DBVDD
DGND
Supply
3
Supply
Digital Ground (return path for both DCVDD and DBVDD)
Audio Interface Bit Clock
4
Digital Input / Output
Digital Input
5
BCLK
DAC Digital Audio Data
6
DACDAT
DACLRC
ADCDAT
ADCLRC
MONOOUT
OUT3
Digital Input / Output
Digital Output
Digital Input / Output
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Audio Interface Left / Right Clock/Clock Out
ADC Digital Audio Data
7
8
Audio Interface Left / Right Clock
9
Mono Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Analogue Output 3 (can be used as Headphone Pseudo Ground)
Right Output 1 (Line or Headphone)
Left Output 1 (Line or Headphone)
ROUT1
LOUT1
HPGND
ROUT2
LOUT2
HPVDD
AVDD
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)
Right Output 1 (Line or Headphone or Speaker)
Left Output 1 (Line or Headphone or Speaker)
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)
Analogue Supply
Analogue Output
Analogue Output
Supply
Supply
Supply
Analogue Ground (return path for AVDD)
Reference Voltage Decoupling Capacitor
Midrail Voltage Decoupling Capacitor
Microphone Bias
AGND
Analogue Output
Analogue Output
Analogue Output
Analogue Input
VREF
VMID
MICBIAS
Right Channel Input 3 or Headphone Plug-in Detection
RINPUT3 /
HPDETECT
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital Input
Left Channel Input 3
24
25
26
27
28
29
30
LINPUT3
RINPUT2
LINPUT2
RINPUT1
LINPUT1
MODE
Right Channel Input 2
Left Channel Input 2
Right Channel Input 1
Left Channel Input 1
Control Interface Selection
Chip Select / Device Address Selection
Digital Input
CSB
Digital Input/Output
Digital Input
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
31
32
SDIN
SCLK
Note:
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
PD, April 2012, Rev 4.1
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