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WM8750CLSEFL 参数 Datasheet PDF下载

WM8750CLSEFL图片预览
型号: WM8750CLSEFL
PDF下载: 下载PDF文件 查看货源
内容描述: 立体声编解码器用于便携式音频应用 [Stereo CODEC for Portable Audio Applications]
分类和应用: 解码器编解码器便携式
文件页数/大小: 65 页 / 733 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8750L  
Production Data  
DIGITAL AUDIO INTERFACE  
The digital audio interface is used for inputting DAC data into the WM8750L and outputting ADC data  
from it. It uses five pins:  
ADCDAT: ADC data output  
ADCLRC: ADC data alignment clock  
DACDAT: DAC data input  
DACLRC: DAC data alignment clock  
BCLK: Bit clock, for synchronisation  
The clock signals BCLK, ADCLRC and DACLRC can be outputs when the WM8750L operates as a  
master, or inputs when it is a slave (see Master and Slave Mode Operation, below).  
Four different audio data formats are supported:  
Left justified  
Right justified  
I2S  
DSP mode  
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the  
Electrical Characteristic section for timing information.  
MASTER AND SLAVE MODE OPERATION  
The WM8750L can be configured as either a master or slave mode device. As a master device the  
WM8750L generates BCLK, ADCLRC and DACLRC and thus controls sequencing of the data  
transfer on ADCDAT and DACDAT. In slave mode, the WM8750L responds with data to clocks it  
receives over the digital audio interface. The mode can be selected by writing to the MS bit (see  
Table 23). Master and slave modes are illustrated below.  
BCLK  
ADCLRC  
DACLRC  
ADCDAT  
DACDAT  
BCLK  
ADCLRC  
DACLRC  
ADCDAT  
DACDAT  
DSP  
ENCODER/  
DECODER  
DSP  
ENCODER/  
DECODER  
WM8750  
CODEC  
WM8750  
CODEC  
Note: The ADC and DAC can run at different sample rates  
Note: The ADC and DAC can run at different sample rates  
Figure 16 Master Mode  
Figure 17 Slave Mode  
Note: For optimum ADC audio performance in Slave Mode, the BCLK input signal edge should  
coincide with the falling edge of MCLK.  
Note that the ADCDAT output pin may be either logic ‘1’ or logic ‘0’ at power-up until data is clocked  
out from the ADC. It is recommended to ensure that any external connection to the ADCDAT pin is  
compatible with the ADCDAT output pin being driven either high or low by the WM8750L until ADC  
data is clocked out. Alternatively, the ADCDAT pin can be tri-stated by setting the TRI bit in Register  
R24 (see Table 35).  
PD, Rev 4.4, August 2012  
40  
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