Production Data
WM8741
REGISTER
ADDRESS
BITS
LABEL
DEFAULT
DESCRIPTION
R0
[4:0]
LAT[4:0]
00 (0dB)
LSBs of attenuation data for left channel in 0.125dB steps. See
Table 25 for details.
DACLLSB
Attenuation
00h
5
UPDATE
0
Attenuation data load control for left channel.
0 = Store LAT[4:0] value but don’t update
1 = Store LAT[4:0] and update attenuation on registers 0-3
R1
[4:0]
5
LAT[9:5]
UPDATE
00 (0dB)
0
MSBs of attenuation data for left channel in 4dB steps. See Table
25 for details.
DACLMSB
Attenuation
01h
Attenuation data load control for left channel.
0 = Store LAT[9:5] value but don’t update
1 = Store LAT[9:5] and update attenuation on registers 0-3
R2
[4:0]
5
RAT[4:0]
UPDATE
00 (0dB)
0
LSBs of attenuation data for right channel in 0.125dB steps. See
Table 25 for details.
DACRLSB
Attenuation
Attenuation data load control for right channel.
0 = Store RAT[4:0] value but don’t update
02h
1 = Store RAT[4:0] and update attenuation on registers 0-3
R3
[4:0]
5
RAT[9:5]
UPDATE
00 (0dB)
0
MSBs of attenuation data for right channel in 4dB step. See Table
25 for details.
DACRMSB
Attenuation
Attenuation data load control for right channel.
0 = Store RAT[9:5] value but don’t update
03h
1 = Store RAT[9:5] and update attenuation on registers 0-3
Table 24 Attenuation Control
Note:
1. The UPDATE bit is not latched. If UPDATE=0, the attenuation value will be written to the pre-latch but not applied to
the relevant DAC. If UPDATE=1, all pre-latched values and the current value being written will be applied on the next
input sample.
DAC OUTPUT ATTENUATION
Registers LAT[9:0] and RAT[9:0] control the left and right channel attenuation. Table 25 shows how
the attenuation levels are configured by the 10-bit words.
L/RAT[9:0]
ATTENUATION LEVEL
000(hex)
0dB
001(hex)
-0.125dB
:
:
:
:
:
:
3FE(hex)
3FF(hex)
-127.75dB
-∞dB (mute)
Table 25 Attenuation Control Levels
ATTENUATION CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect. Right channels register settings are preserved regardless of the
status of ATC.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4
Volume Control
04h
2
ATC
0
Attenuator Control Mode:
0 = Right channels use Right
attenuation
1 = Right Channels use Left
Attenuation
Table 26 Attenuator Control Mode
PD, Rev 4.2, October 2009
31
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
