WM8741
Production Data
MCLK/LRCLK RATIO CONTROL (NORMAL PCM MODE)
The ratio of MCLK/LRCLK can be programmed directly or auto-detected.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
Mode Control 1
07h
[4:2]
SR[3:0]
000
MCLK to LRCLK sampling rate ratio
control (Normal PCM Mode):
000 = auto detect sample rate
001 = 128fs
010 = 192fs
011 = 256fs
100 = 384fs
101 = 512fs
110 = 768fs
111 = reserved
Table 21 MCLK/LRCLK Ratio Control (Normal PCM Mode)
8FS MODE
8FS Mode allows the use of custom digital filters by bypassing the WM8741 internal digital filters.
When MODE8X is set, the PCM data input to the WM8741 is applied only to the digital volume
control and then the analogue section of the DAC system, bypassing the digital filters.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
8FS mode select:
R7
Format Control
07h
7
MODE8X
0
0 = Normal operation
1 = 8FS mode (digital filters
bypassed)
Table 22 8FS Mode Control
MCLK/LRCLK RATIO CONTROL (8FS MODE)
In 8FS mode the choice of clock ratios and sampling rates is limited – see Table 12 for details.
Autodetect of MCLK/LRCLK ratio is not available in 8FS mode and must be set manually by the user
for correct operation.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
Mode Control 1
07h
[4:2]
SR[2:0]
000
MCLK to LRCLK sampling rate ratio
control (8FS Mode):
000 = reserved
001 = 512fs
010 = 768fs
011 to 111 = reserved
Table 23 MCLK/LRCLK Ratio Control (8FS Mode)
ATTENUATION CONTROL
Each DAC channel can be attenuated digitally before being applied to the digital filter. Attenuation is
set to 0dB by default but can be set between 0dB and -127.5dB in 0.125dB steps using the ten
attenuation control bits LAT[4:0], LAT[9:5], RAT[4:0] and RAT[9:5].
All attenuation registers are double latched allowing new values to be pre-latched to both channels
before being updated synchronously. Setting the UPDATE bit on any attenuation write will cause all
pre-latched values to be immediately applied to the DAC channels.
PD, Rev 4.2, October 2009
30
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
