Production Data
WM8741
DSD MODE
The WM8741 supports DSD input bitstreams at 64x the oversampling rate. The data is supplied at a
rate of 64 bits per normal word clock. In DSD, no word clock is provided.
The WM8741 supports two channels of bitstream or DSD audio. Data bitstreams and the 64fs clock
are supplied to pins 1, 22 and 3 respectively. The MODESEL[1:0] register bits control whether the
device operates in DSD direct, DSD plus or PCM modes.
DSD DIRECT
In DSD Direct mode the internal digital filters are bypassed, the input bitstream data is subjected to
the minimal possible processing and is applied directly to the switched capacitor stage of the DAC
system. Using this mode provides the purest possible representation of a DSD stream.
It is normally desirable to use an external analogue post-DAC analogue filter to combine the
differential outputs of the DAC and remove high frequency energy from the output. This is
particularly important in the case of DSD operation due to the presence of high frequency energy
which is a result of the aggressive high order noise shaping used in the creation of the modulated
DSD datastream.
DSD PLUS MODE
In DSD Plus mode the DSD data can be filtered in a similar manner to the data in the PCM path.
The DSD Plus filters are selected using register bits DSDFILT[1:0]. DSD Plus mode is not available
under hardware control.
Although DSD Plus mode requires that the bitstream is more heavily processed than DSD Direct, the
advantage is that DSD Plus mode reduces the high frequency energy which is a result of the
aggressive high order noise shaping used in the creation of the modulated DSD datastream. This
means that a less aggressive, lower order, analogue filter can be used at the output. Furthermore
the slew-rate requirements of the op-amps can be relaxed compared to DSD direct mode, due to the
reduction in high frequency energy.
DSD DIGITAL AUDIO INTERFACE
DSD audio data is input to the WM8741 via the DSD digital audio interface. Two interface formats
are supported:
•
•
Uni-phase
Bi-phase
To use this interface apply left data on input pin 1 (LRCLK/DSDL) and pin 22 (OSR/DSDR). A DSD
clock is also required, running at 64FS, and should be applied to pin 3 (BCLK/DSD64CLK).
Figure 22 Uni-phase DSD Mode Timing Diagram
PD, Rev 4.2, October 2009
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
