WM8740
Production Data
tSCKIL
SCKI
tSCKIH
tSCKY
Figure 2 System Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
System clock pulse width high
System clock pulse width low
System clock cycle time
tSCKIH
tSCKIL
tSCKY
10
10
27
ns
ns
ns
tMLL
tMHH
ML/I2S
tMCY
tMCH tMCL
tMLD
tMLS
MC/DM1
MD/DM0
tMDS
tMDH
LSB
Figure 3 Program Register Input Timing – SPI Compatible Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MC/DM1 pulse cycle time
MC/DM1 pulse width low
MD/DM0 pulse width high
MD/DM0 set-up time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMHH
tMLS
tMLD
80
32
32
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC/DM1 hold time
ML/I2S pulse width low
ML/I2S pulse width high
ML/I2S set-up time
ML/I2S delay from MC
PD Rev 4.0 April 2004
8
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
