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WM8740_04 参数 Datasheet PDF下载

WM8740_04图片预览
型号: WM8740_04
PDF下载: 下载PDF文件 查看货源
内容描述: 24位高性能192kHz的立体声DAC [24-bit, High Performance 192kHz Stereo DAC]
分类和应用:
文件页数/大小: 24 页 / 449 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8740  
Production Data  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Analogue Output Levels  
Output level differential  
Into 10k, full scale 0dB,  
2
1.32  
1
VRMS  
VRMS  
kΩ  
(5V supply)  
Into 10k, full scale 0dB,  
(3.3V supply)  
Minimum resistance load  
To midrail or AC coupled  
(5V supply)  
To midrail or AC coupled  
(3.3V supply)  
600  
Maximum capacitance load  
Output DC level  
5V or 3.3V  
100  
pF  
V
AVDD/2  
Reference Levels  
Potential divider resistance  
10  
AVDD/2  
2.2  
kΩ  
AVDD to VMIDL/VMIDR and  
VMIDL/VMIDR to AGND  
Voltage at VMIDL/VMIDR  
POR (Power-On Reset)  
POR threshold  
V
Notes: 1.  
Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’  
weighted over a 20Hz to 20kHz bandwidth.  
2.  
All performance measurements done with 20kHz low pass filter. Failure to use such a filter will result in higher  
THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low  
pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.  
LRCIN  
tBCH  
tBCL  
tLB  
BCKIN  
DIN  
tBCY  
tBL  
tDS  
tDH  
Figure 1 Audio Data Input Timing  
Test Conditions  
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, SCKI = 256fs unless otherwise stated.  
PARAMETER  
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Audio Data Input Timing Information  
BCKIN pulse cycle time  
BCKIN pulse width high  
BCKIN pulse width low  
tBCY  
tBCH  
tBCL  
tBL  
100  
40  
ns  
ns  
ns  
ns  
40  
BCKIN rising edge to  
LRCIN edge  
20  
LRCIN rising edge to  
BCKIN rising edge  
tLB  
20  
ns  
DIN setup time  
DIN hold time  
tDS  
tDH  
20  
20  
ns  
ns  
PD Rev 4.0 April 2004  
7
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