WM8740
Production Data
SOFTWARE DIFFERENTIAL MONO MODE
To control the WM8740 in software differential mode register M4 must be written to. A ‘key’ register
write must be made to register M2 to allow access to register M4 which is ‘locked’ as default. Bits B5
to B8 of register M2 must be set to ‘1’ (0x01e0).
With register M4 ‘unlocked’, bits B4 and B5 may be used to set the required differential output mode;
normal stereo, reversed stereo, mono left or mono right, as shown in Table 18.
DIFF[1:0]
B[5:4])
00
DIFFERENTIAL OUTPUT MODE
Stereo
10
Stereo reverse.
01
Mono left – differential outputs.
VOUTLP (17) is left channel.
VOUTLN (16) is left channel inverted.
VOUTRP (12) is left channel inverted.
VOUTRN (13) is left channel.
Mono right – differential outputs.
VOUTLP (17) is right channel inverted.
VOUTLN (16) is right channel.
VOUTRP (12) is right channel.
VOUTRN (13) is right channel inverted.
11
Table 18 Differential Output Modes
Using these controls a pair of WM8740 devices may be used to build a dual differential stereo
implementation with higher performance and differential output.
Note: DIFFHW mode pin may be used to achieve the same result by hardware means.
CLOCK LOSS DETECTOR DISABLE
CDD (REG4, B6)
L
Clock loss detector on
Clock loss detector off
R
Table 19 Clock Loss Detector Disable
When the system clock is inactive for approximately 100µs, the clock loss detector circuit detects the
loss of clock and the analogue circuitry is forced into a mute condition and the digital filters reset.
Setting the CDD bit disables this behaviour.
PD Rev 4.0 April 2004
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
