Production Data
WM8737L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
TMCLKL
TMCLKH
TMCLKY
13
13
26
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
tDL
ADCLRC
(Output)
tDDA
ADCDAT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC propagation delay from BCLK falling edge
ADCDAT propagation delay from BCLK falling edge
tDL
0
0
10
10
ns
ns
tDDA
AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
ADCLRC
tLRSU
tLRH
tDD
ADCDAT
Figure 3 Digital Audio Data Timing – Slave Mode
PD, Rev 4.4, January 2012
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
