WM8731 / WM8731L
Production Data
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
ADCLRC
WM8731
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Note: The ADC and DAC can run at different rates
Figure 5 Slave Mode Connection
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DACDAT
ADCDAT
tDD
tDH
Figure 6 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tLRSU
DACLRC/ADCLRC hold
time from BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DACDAT set-up time to
BCLK rising edge
DACDAT hold time from
BCLK rising edge
tDH
PD, Rev 4.9, October 2012
17
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
