WM8731 / WM8731L
Production Data
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8731
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Note: ADC and DAC can run at different rates
Figure 3 Master Mode Connection
BCLK
(Output)
tDL
ADCLRC
DAC/LRC
(Outputs)
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 4 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
ADCDAT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
35
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
10
10
DACDAT hold time from
BCLK rising edge
PD, Rev 4.9, October 2012
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
