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WM8728 参数 Datasheet PDF下载

WM8728图片预览
型号: WM8728
PDF下载: 下载PDF文件 查看货源
内容描述: 24位, 192kHz的立体声DAC,具有音量控制和DSD支持 [24-bit, 192kHz Stereo DAC with Volume Control and DSD Support]
分类和应用:
文件页数/大小: 28 页 / 267 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8728  
Product Preview  
HARDWARE DSD MODE  
DSD mode is selected by taking the SCKDSD pin high whilst the MODE pin is low. In this mode  
the internal digital filters are bypassed, and the already modulated bitstream data is applied  
directly to the Switched Capacitor DAC filter where it is converted and lowpass filtered, see Figure  
26 to Figure 29.  
Two formats are supported for data transfer, MONOPHASE or BIPHASE MODULATED.  
In Monophase mode, DSD data is simply clocked into the device using the rising edge of the 64fs  
MCLK signal.  
In Biphase mode, the data is supplied in Manchester encoded form (a bit transition occurs during  
every data bit, which shapes the spectral energy minimising corruption of the analogue outputs).  
A secondary clock BCKIN, at 128fs is used to simplify data recovery, the data simply being  
clocked with the falling edge of BCKIN when MCLK is at logic low (0V).  
See Figure 3 and Figure 4 for details of DSD interface timing.  
HARDWARE CONTROL MODES  
When the MODE pin is held low, the following hardware modes of operation are available.  
MUTE AND AUTOMUTE OPERATION  
In both hardware and software modes, pin 17 (MUTEB) controls the selection of MUTE directly,  
and can be used to enable and disable the automute function. This pin becomes an output when  
left floating and indicates infinite ZERO detect (IZD) see also pin 5 (ZERO).  
MUTEB PIN  
DESCRIPTION  
0
1
Mute DAC channels  
Normal Operation  
Floating  
Enable IZD, MUTEB becomes an output to indicate when IZD occurs.  
L=IZD detected, H=IZD not detected.  
Table 2 Mute and Automute Control  
Figure 12 shows the application and release of MUTE whilst a full amplitude sinusoid is being  
played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace)  
begins to decay exponentially from the DC level of the last input sample. The output will decay  
towards VMID with a time constant of approximately 64 input samples. When MUTE is de-  
asserted, the output will restart almost immediately from the current input sample.  
1.5  
1
0.5  
0
-0.5  
-1  
-1.5  
-2  
-2.5  
0
0.001  
0.002  
0.003  
0.004  
0.005  
0.006  
Time(s)  
WOLFSON MICROELECTRONICS LTD  
PP Rev 1.2 April 2001  
15  
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