WM8728
Production Data
POWER SUPPLY TIMING
Figure 3 Power Supply Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD set up time to AVDD
rising edge
TPSU
Measured from DVDD=+2.4V to
AVDD=+0.7V
100
µs
POWER ON RESET (POR)
The WM8728 has an internal power-on-reset (POR) circuit which is used to reset the digital logic
into a default state after power up. A block diagram of the reset circuit is shown in Figure 4
Figure 4 Block Diagram of Power-On-Reset Circuit
PD, Rev 4.6 August 2008
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
