WM8728
Production Data
MPU 3-WIRE INTERFACE TIMING
Figure 8 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCK rising edge to LATI2S
rising edge
tSCS
40
ns
SCK pulse cycle time
tSCY
tSCL
80
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK pulse width low
SCK pulse width high
tSCH
tDSU
tDHO
tCSL
SDIDEM to SCK set-up time
SCK to SDIDEM hold time
LATI2S pulse width low
LATI2S pulse width high
LATI2S rising to SCK rising
CSBIWL to LATI2S set-up time
LATI2S to CSBIWL hold time
tCSH
tCSS
tCSSU
tCSSH
PD, Rev 4.6, August 2008
12
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
