WM8720
Production Data
DAC OUTPUT CONTROL
Bits 5, 6, 7 and 8 (PL[3:0]) of register 2 are used to control the output format as shown in Table 11.
PL3
PL2
PL1
PL0
LEFT
RIGHT
NOTE
OUTPUT
OUTPUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
Mute both channels
L
MUTE
R
(L + R)/2
MUTE
L
MUTE
MUTE
L
L
R
L
Reverse channels
Stereo mode
(L + R)/2
MUTE
L
L
R
R
R
R
(L + R)/2
MUTE
L
R
(L + R)/2
(L + R)/2
(L + R)/2
(L + R)/2
R
(L + R)/2
Mono mode
Table 11 Programmable DAC Output Format
SERIAL PROTOCOL
Bits 0 (I2S) and 1 (LRP) of register 3 are used to control the input data format completely. A low on
bit 0 (I2S = 0) sets the format to Normal (MSB-first, right justified Japanese format), whilst a high
(I2S = 1) sets the format to I2S (Philips serial data protocol).
POLARITY OF LRCIN SELECT
Bit 1 (LRP) of register 3 is used to control the polarity of LRCIN (sample rate clock). When bit 1 is
low (LRP = 0), left channel data is assumed when LRCIN is in a high phase and right channel data
is assumed when LRCIN is in a low phase. When bit 1 is high (LRP = 1), the polarity assumption
is reversed.
INTERFACE CLOCKS AND SAMPLING RATES
Bits 6 (SF0) and 7 (SF1) of register 3 are used to control the sampling frequency, as shown in
Table 12.
SF0
0
SF1
0
SAMPLING FREQUENCY
44.1 kHz group
22.05 / 44.1 / 88.2 kHz
24 / 48 / 96 kHz
16 / 32 / 64 kHz
Not defined
0
1
48 kHz group
32 kHz group
Reserved
1
0
1
1
Table 12 Sampling Frequencies
INFINITE ZERO DETECTION
Bit 8 (IZD) in register 3 controls operation of the automute function. If IZD (Infinite Zero Detect) is
high, 1024 consecutive zero audio samples will force the output to zero. See Figure 6. Note that the
control of pin MUTE also affects automute operation. To turn off automute, pin MUTE must be held
low as well as IZD being low (default).
PD Rev 4.0 February 2005
14
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