WM8718
Production Data
3-WIRE SERIAL CONTROL INTERFACE TIMING
tCSL
tCSH
LATCH
tSCY
tCSS
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to LATCH
rising edge
tSCS
40
ns
SCLK pulse cycle time
SCLK pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
LATCH pulse width low
LATCH pulse width high
LATCH rising to SCLK rising
PD Rev 4.1 March 2004
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
