Production Data
WM8711L
DIGITAL AUDIO INTERFACE – SLAVE MODE
tBCH
tBCL
BCLK
(Input)
tBCY
DACLRC
(Input)
tLRSU
tDS
tLRH
DACDAT
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC set-up time to
BCLK rising edge
tLRSU
DACLRC hold time from
BCLK rising edge
tLRH
tDS
10
10
10
ns
ns
ns
DACDAT set-up time to
BCLK rising edge
DACDAT hold time from
BCLK rising edge
tDH
MPU INTERFACE TIMING
tCSL
tCSH
CSB
tCSS
tSCY
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 4 Program Register Input Timing - 3-Wire MPU interface Timing
PD, Rev 4.5, August 2011
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
