WM8711L
Production Data
MASTER CLOCK TIMING
tXTIL
MCLK
tXTIH
tXTIY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width
high
tXTIH
tXTIL
tXTIY
18
18
ns
ns
ns
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
54
40:60
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
(Output)
tDL
DACLRC
(Output)
tDLT
tDHT
DACDAT
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
tDL
0
10
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
tDST
tDHT
10
10
DACDAT hold time from
BCLK rising edge
PD, Rev 4.5, August 2011
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
