WM8711BL
Production Data
MASTER AND SLAVE MODE OPERATION
The WM8711BL can be configured as either a master or slave mode device. As a master mode
device the WM8711BL controls sequencing of the data and clocks on the digital audio interface. As a
slave device the WM8711BL responds with data to the clocks it receives over the digital audio
interface. The mode is set with the MS bit of the control register as shown in Table 9.
REGISTER ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
0000111
6
MS
0
Digital Audio Interface
Format
Table 9 Programming Master/Slave Modes
As a master mode device the WM8711BL controls the sequencing of data transfer (DACDAT) and
output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from
the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 18.
DACDAT is always an input to the WM8711BL independent of master or slave mode.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 18 Master Mode
As a slave device the WM8711BL sequences the data transfer (DACDAT) over the digital audio
interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 19.
BCLK
DSP
DECODER
WM8711
DAC
DACLRC
DACDAT
Figure 19 Slave Mode
Note that the WM8711BL relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section
for detailed information.
PD, Rev 4.2, December 2011
2644
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
