WM8706
Production Data
MPU INTERFACE TIMING
CSBIWO
MLIIS
tCSSU
tCSSH
tCSL
tCSH
tSCY
tCSS
tSCS
tSCH
tSCL
MCDM1
MDDM0
LSB
tDSU
tDHO
Figure 3 Program Register Input Timing - 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
MCDM1 rising edge to MLIIS
rising edge
tSCS
40
ns
MCDM1 pulse cycle time
MCDM1 pulse width low
MCDM1 pulse width high
MDDM0 to MCDM1 set-up time
MCDM1 to MDDM0 hold time
MLIIS pulse width low
tSCY
tSCL
80
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Ns
ns
tSCH
tDSU
tDHO
tCSL
MLIIS pulse width high
tCSH
tCSS
tCSSU
tCSSH
MLIIS rising to SCLK rising
CSBIWO to MLIIS set-up time
MLIIS to CSBIWO hold time
PD Rev 4.1 July 2005
9
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
