WM8706
Production Data
MASTER CLOCK TIMING
tXTIL
XTI
tXTIH
tXTIY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Master Clock Timing Information
XTI Master clock pulse width high
XTI Master clock pulse width low
XTI Master clock cycle time
XTI Duty cycle
tXTIH
tXTIL
tXTIY
13
13
ns
ns
ns
26
40:60
60:40
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
LRCIN
DIN
tBCY
tLRSU
tDS
tLRH
tDH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD, DVDD = 5V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, XTI = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCKIN cycle time
tBCY
tBCH
tBCL
40
16
16
8
ns
ns
ns
ns
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
tLRSU
LRCIN hold time from
BCKIN rising edge
tLRH
tDS
8
8
8
ns
ns
ns
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
tDH
PD Rev 4.1 July 2005
8
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