Production Data
WM8580
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
Attenuation
DACR 3
8
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store RDA3 in intermediate latch (no change to output)
1 = Apply RDA3 and update attenuation on all channels
19h
R28
7:0
8
MASTDA[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation control for all DAC channels in 0.5dB steps.
See Table 23
Master Digital
Attenuation
Not latched
Controls simultaneous update of all Attenuation Latches
0 = Store gain in intermediate latch (no change to output)
1 = Apply gain and update attenuation on all channels
1Ch
R29
0
1
AMUTEL
AMUTER
0
0
ADC Mute select
ADC
Control 1
0 = Normal Operation
1 = mute ADC left
1Dh
ADC Mute select
0 = Normal Operation
1 = mute ADC right
2
AMUTEALL
ADCOSR
0
ADC Mute select
0 = Normal Operation
1 = mute both ADC channels
ADC oversample rate select
0 = 128/64 x oversampling
1 = 64/32 x oversampling
ADC high-pass filter disable:
0 = high-pass filter enabled
1 = high-pass filter disabled
3
0
4
ADCHPD
0
7:5
ADCRATE[2:0]
010
ADC Rate Control (only used when the S/PDIF Transmitter is the
only interface sourcing the ADC)
000 = 128fs
001 = 192fs
010 = 256fs
011 = 384fs
100 = 512fs
101 = 768fs
110 = 1152fs
8
VMIDSEL
1
VMID Impedance Selection
0 = High impedance, power saving
1 = Low impedance, fast power-on
S/PDIF Transmitter Data Source
00 = S/PDIF received data (see REAL_THROUGH)
01 = ADC digital output data.
R30
SPDTXCHAN 0
1Eh
1:0
TXSRC[1:0]
10
10 = Secondary Audio Interface
11 = Audio Interface received data
2
3
OVWCHAN
0
0
Only used if TXSRC==00. Overwrites the ‘through-path’ Channel
Bit with values determined by the channel-bit control registers.
0 = Channel data equal to recovered channel data.
1 = Channel data taken from channel status registers.
S/PDIF Through Mode Control
REAL_
THROUGH
0 = SPDIFOP pin sources output of S/PDIF Transmitter
1 = SPDIFOP pins sources output of S/PDIF IN Mux
PD Rev 4.3 August 2007
83
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
