Production Data
REGISTER
WM8580
BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
R49
0
AUDIO_N
-
Linear PCM Identification
0 = Data word represents audio PCM samples.
SPDSTAT
31h
1 = Data word does not represent audio PCM samples.
(read-only)
1
PCM_N
-
Indicates that non-audio code (defined in IEC-61937)
has been detected.
0 = Sync code not detected.
1 = Sync code detected – received data is not audio
PCM.
2
3
CPY_N
-
-
Recovered Channel Status bit-2 (active low).
0 = Copyright is asserted for this data.
1 = Copyright is not asserted for this data.
Recovered Channel Status bit-3
0 = Recovered S/PDIF data has no pre-emphasis.
1 = Recovered S/PDIF data has pre-emphasis
Indicates recovered S/PDIF clock frequency:
00 = Invalid
DEEMPH
5:4
REC_FREQ
[1:0]
--
01 = 96kHz / 88.2kHz
10 = 48kHz / 44.1kHz
11 = 32kHz
6
UNLOCK
-
Indicates that the S/PDIF Clock Recovery circuit is
unlocked or that the input S/PDIF signal is not present.
0 = Locked onto incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream or the
incoming S/PDIF stream is not present.
Table 63 S/PDIF Status Register
The interrupt and update signals used to generate INT_N can be masked as necessary. The MASK
register bit prevents flags from asserting INT_N and from updating the Interrupt Status Register
(R43). Masked flags update the S/PDIF Status Register (R49).
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R37
INTMASK
25h
8:0
MASK[8:0]
000000000
When a flag is masked, it does not update the Interrupt
Status Register or assert INT_N.
0 = unmask, 1 = mask.
MASK[0] = mask control for UPD_UNLOCK
MASK[1] = mask control for INT_INVALID
MASK[2] = mask control for INT_CSUD
MASK[3] = mask control for INT_TRANS_ERR
MASK[4] = mask control for UPD_AUDIO_N
MASK[5] = mask control for UPD_PCM_N
MASK[6] = mask control for UPD_CPY_N
MASK[7] = mask control for UPD_DEEMPH
MASK[8] = mask control for UPD_REC_FREQ
Table 64 Interrupt Mask Control Register
PD Rev 4.3 August 2007
65
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
