WM8580
Production Data
REGISTER
ADDRESS
BIT
LABEL
CHANNEL
STATUS
BIT
DEFAULT
DESCRIPTION
R46
SPDRXCHAN 3
2Eh
3:0
SRCNUM
[3:0]
19:16
-
Indicates S/PDIF source number.
Refer to S/PDIF specification IEC60958-3 for
details.
5:4
7:6
CHNUM1[1:0]
21:20
-
Channel number for sub-frame 1.
(read-only)
00 = Take no account of channel number
(channel 1 defaults to left DAC)
01 = channel 1 to left channel
10 = channel 1 to right channel
Channel number for sub-frame 2.
CHNUM2[1:0]
23:22
00 = Take no account of channel number
(channel 2 defaults to left DAC)
01 = channel 2 to left channel
10 = channel 2 to right channel
Table 58 S/PDIF Receiver Channel Status Register 3
REGISTER
ADDRESS
BIT
LABEL
CHANNEL
STATUS
BIT
DEFAULT
DESCRIPTION
R47
SPDRXCHAN 4
2Fh
3:0
FREQ[3:0]
27:24
-
Sampling Frequency Indicated.
Refer to S/PDIF specification IEC60958-3 for
details.
5:4
CLKACU[1:0]
29:28
-
Clock Accuracy of received clock.
00 = Level II
(read-only)
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
Table 59 S/PDIF Receiver Channel Status Register 4
REGISTER
ADDRESS
BIT
LABEL
CHANNEL
STATUS
BIT
DEFAULT
DESCRIPTION
R48
SPDRXCHAN 5
30h
0
MAXWL
32
-
Maximum Audio sample word length
0 = 20 bits
1 = 24 bits
(read-only)
3:1
RXWL[2:0]
35:33
-
Audio Sample Word Length.
000: Word Length Not Indicated
RXWL[2:0]
001
MAXWL==1
20 bits
MAXWL==0
16 bits
010
22 bits
18 bits
100
23 bits
19 bits
101
24 bits
20 bits
110
21 bits
17 bits
All other combinations are reserved and may
give erroneous operation. Data will be
truncated internally when these bits are set
unless WL_MASK is set.
7:4
ORGSAMP
[3:0]
39:36
-
Original Sampling Frequency. Refer to
S/PDIF specification IEC60958-3 for details.
0000 = original sampling frequency not
indicated
Table 60 S/PDIF Receiver Channel Status Register 5
PD Rev 4.3 August 2007
62
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
