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WM8533 参数 Datasheet PDF下载

WM8533图片预览
型号: WM8533
PDF下载: 下载PDF文件 查看货源
内容描述: 24位192kHz的立体声DAC,具有2Vrms的接地参考输出线 [24-bit 192kHz Stereo DAC with 2Vrms Ground Referenced Line Output]
分类和应用:
文件页数/大小: 41 页 / 742 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8533  
ABSOLUTE MAXIMUM RATINGS  
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously  
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given  
under Electrical Characteristics at the test conditions specified.  
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically  
susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling  
and storage of this device.  
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage  
conditions prior to surface mount assembly. These levels are:  
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.  
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.  
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.  
The Moisture Sensitivity Level for each package type is specified in Ordering Information.  
CONDITION  
MIN  
-0.3V  
MAX  
+4.5V  
AVDD, LINEVDD, DBVDD  
Voltage range digital inputs  
Voltage range analogue inputs  
Temperature range, TA  
AGND -0.3V  
AGND -0.3V  
-40°C  
DBVDD +0.3V  
AVDD +0.3V  
+85°C  
Storage temperature after soldering  
-65°C  
+150°C  
RECOMMENDED OPERATING CONDITIONS  
PARAMETER  
SYMBOL  
AVDD, LINEVDD  
DBVDD  
TEST CONDITIONS  
MIN  
2.97  
1.62  
TYP  
MAX  
3.63  
3.63  
UNIT  
Analogue supply range  
Digital buffer supply range  
Ground  
3.3  
V
V
V
AGND, LINEGND  
0
Notes  
1. Analogue grounds must always be within 0.3V of each other.  
2. LINEVDD and AVDD must always be within 0.3V of each other.  
PD, July 2012, Rev 4.0  
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