WM8522
Production Data
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
2
LRP
0
In left/right/I2S Modes:
LRCLK Polarity (normal)
0 : Normal LRCLK polarity
1: Inverted LRCLK polarity
In DSP Mode:
0 : DSP mode A
1: DSP mode B
3
BCP
0
BCLK Polarity (DSP Modes):
0: Normal BCLK polarity
1: Inverted BCLK polarity
Input Word Length:
00 : 16 bit data
5:4
IWL[5:4]
00
01: 20 bit data
10: 24 bit data
11: 32 bit data
8:6
PHASE
[8:6]
000
Bit
0
DAC
Phase
DAC1L/R
DAC2L/R
DAC3L/R
1 = invert
1 = invert
1 = invert
1
2
R4
7:0
8
LDA2[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See
Table 16
(04h)
Digital
Attenuation
DACL2
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA2 in intermediate latch (no change to output)
1: Store LDA2 and update attenuation on all channels.
R5
7:0
8
RDA2[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Right channel DACR2 in 0.5dB steps.
See Table 16
(05h)
Digital
Attenuation
DACR2
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA2 in intermediate latch (no change to output)
1: Store RDA2 and update attenuation on all channels.
R6
7:0
8
LDA3[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See
Table 16
(06h)
Digital
Attenuation
DACL3
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store LDA3 in intermediate latch (no change to output)
1: Store LDA3 and update attenuation on all channels.
R7
7:0
8
RDA3[7:0]
UPDATE
11111111
(0dB)
Digital Attenuation data for Right channel DACR3 in 0.5dB steps.
See Table 16
(07h)
Digital
Attenuation
DACR3
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store RDA3 in intermediate latch (no change to output)
1: Store RDA3 and update attenuation on all channels.
R8
7:0
8
MASTDA
[7:0]
11111111
(0dB)
Digital Attenuation data for all DAC channels in 0.5dB steps. See
Table 16
(08h)
Master
Digital
Attenuation
UPDATE
Not latched
Controls simultaneous update of all Attenuation Latches
0: Store gain in intermediate latch (no change to output)
1: Store gain and update attenuation on all channels.
(all channels)
R9
0
ZCD
0
DAC Digital Volume Zero Cross Enable:
0: Zero cross detect enabled
(09h)
DAC Mute
1: Zero cross detect disabled
2:1
5:3
DZFM[1:0]
00
Zero flag/mute decode. See Table 11, Table 12 and Table 13 for
details.
DMUTE
[2:0]
000
DAC Soft Mute Select. See Table 10 for details.
PD Rev 4.0 July 2006
32
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
