Production Data
WM8522
DACPD [2:0]
000
DAC CHANNEL 1
Active
DAC CHANNEL 2
Active
DAC CHANNEL 3
Active
Active
001
DISABLE
Active
Active
010
DISABLE
DISABLE
Active
Active
011
DISABLE
Active
Active
100
DISABLE
DISABLE
DISABLE
DISABLE
101
DISABLE
Active
Active
110
DISABLE
DISABLE
111
DISABLE
Table 15 DAC Disable Control
MASTER POWERDOWN
This control bit powers down the references for the whole chip. Therefore for complete powerdown,
all DACs should be powered down first before setting this bit.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
Master Power Down Bit:
0: Not powered down
1: Powered down
4
PWRDNALL
0
Interface Control
MASTER MODE SELECT
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK
and BCLK are outputs and are generated by the WM8522. In Slave mode LRCLK and BCLK are
inputs to WM8522.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
5
MS
0
DAC Audio Interface Master/Slave
Mode Select:
Interface Control
0: Slave mode
1: Master mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8522 generates LRCLK and BCLK. These clocks are derived from the
master clock and the ratio of MCLK to LRCLK is set by RATE.
REGISTER ADDRESS
0001010
BIT
LABEL
DEFAULT
DESCRIPTION
Master Mode
8:6 RATE [2:0]
010
Interface Control
MCLK:LRCLK Ratio Select:
000: 128fs
001: 192fs
010: 256fs
011: 384fs
100: 512fs
101: 768fs
PD Rev 4.0 July 2006
27
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
