WM8522
Production Data
MPU INTERFACE TIMING
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
SCLK/IWL rising edge to CSB/I2S rising edge
SCLK/IWL pulse cycle time
SYMBOL
SCS 6
MIN
0
TYP
MAX
UNIT
t
ns
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
30
30
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
SCLK/IWL pulse width low
SCLK/IWL pulse width high
SDIN/DM to SCLK/IWL set-up time
SCLK/IWL to SDIN/DM hold time
CSB/I2S pulse width low
CSB/I2S pulse width high
CSB/I2S rising to SCLK/IWL rising
Table 4 3-Wire SPI Compatible Control Interface Input Timing Information
PD Rev 4.0 July 2006
10
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
