WM8501
Pre-Production
MASTER CLOCK TIMING
tMCLKL
MCLK
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
tMCLKH
tMCLKL
tMCLKY
8
8
ns
ns
ns
20
40:60
1.5
60:40
12
Time from MCLK stopping to power
down.
µs
DIGITAL AUDIO INTERFACE
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
40
ns
BCLK pulse width high
BCLK pulse width low
ns
ns
16
16
LRCLK set-up time to BCLK
rising edge
tLRSU
8
8
8
8
ns
ns
ns
ns
LRCLK hold time from
BCLK rising edge
tLRH
tDS
DIN set-up time to BCLK
rising edge
DIN hold time from BCLK
rising edge
tDH
PP Rev 3.1 May 2006
8
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