WM8501
Pre-Production
DC ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
AVDD
TEST CONDITIONS
MIN
4.5
TYP
MAX
5.5
UNIT
V
Analogue supply range
Digital supply range
Ground
DVDD
2.7
5.5
V
AGND, DGND
0
9
V
Analog supply current
Digital supply current
AVDD = 5V
DVDD = 5V
mA
mA
mA
mA
8
DVDD = 3.3V
AVDD=DVDD=5V
4.5
0.01
Power down current (note 4)
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = 5V, DVDD = 3.3V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (TTL Levels)
Input LOW level
VIL
VIH
0.8
V
V
Input HIGH level
2.0
Output LOW
VOL
VOH
I
OL = 2mA
DGND + 0.3V
V
V
Output HIGH
I
OH = 2mA
DVDD – 0.3V
Analogue Reference Levels
Reference voltage (VMID)
Potential divider resistance
AVDD/2
50
V
RCAP
AVDD to VMID and
VMID to GND
kΩ
DAC Output (Load = 10kΩ. 50pF)
0dBFs Full scale output voltage
At DAC outputs
1.6 x
AVDD/5
1.7 x
AVDD/5
100
1.8 x
AVDD/5
Vrms
dB
Signal to Noise Ratio (Note
5,6,7)
SNR
A-weighted,
@ fs = 48kHz
A-weighted
@ fs = 96kHz
A-weighted
90
97
97
dB
dB
@ fs = 192kHz
Dynamic Range (Note 2, 6)
DNR
THD
A-weighted, -60dB full
scale input
90
100
-88
dB
Total Harmonic Distortion
(Note 7)
1kHz, Load = 10kΩ,
-78
dB
0dBFS
DAC channel separation
Analogue Output Levels
Output level
93
dB
Load = 10kΩ, 0dBFS
1.7
1
Vrms
Gain mismatch
%FSR
channel-to-channel
Minimum resistance load
To midrail or a.c.
coupled
16
Ω
Output d.c. level
AVDD/2
V
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth.
2. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a
filter will result in higher THD and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics.
The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.
3. VMID pin decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
4. Power down occurs 1.5µs after MCLK is stopped.
PP Rev 3.1 May 2006
w
6