WM8501
Production Data
1/fs
Max 4 BCLK's
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
NO VALID DATA
1
2
1
2
1
DIN
15
15
16
16
MSB
LSB
Input Word Length (16 bits)
Figure 6 DSP Mode B Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8501 supports audio sampling rates from 128fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The
master clock is used to operate the digital filters and the noise shaping circuits.
The WM8501 has a master clock detection circuit that automatically determines the relation
between the master clock frequency and the sampling rate (to within +/- 8 master clocks). If there
is a greater than 8 clocks error, the interface shuts down the DAC and mutes the output. The
master clock should be synchronised with LRCLK, although the WM8501 is tolerant of phase
differences or jitter on this clock.
SAMPLING
RATE
MASTER CLOCK FREQUENCY (MHz) (MCLK)
128fs
192fs
256fs
384fs
512fs
768fs
(LRCLK)
32kHz
4.096
5.6448
6.144
6.144
8.467
8.192
11.2896
12.288
24.576
12.288
16.9344
18.432
36.864
16.384
22.5792
24.576
24.576
33.8688
36.864
44.1kHz
48kHz
9.216
96kHz
12.288
24.576
18.432
36.864
Unavailable Unavailable
192kHz
Unavailable Unavailable Unavailable Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
The WM8501 is hardware programmable providing the user with options to select input audio data
format, de-emphasis and mute.
ENABLE OPERATION
Pin 4 (ENABLE) controls the operation of the chip. If ENABLE is low the device is held in a low
power state. If this pin is held high the device is powered up.
To ensure correct operation it is essential that there is a low to high transition on the ENABLE pin
after digital supplies have come on. This can be achieved by providing the ENABLE signal from
an external controller chip or by means of a simple RC network on the ENABLE pin. See
“Recommended External Components” in the “Application Information” section at the end of this
datasheet.
Note that the ENABLE pin should not be used as a mute pin or to temporarily silence the DAC
(between tracks of a CD for example). The ENABLE pin is not intended to be used as a mute
control but to allow entry into low power mode. Disabling the device via the ENABLE pin has the
effect of powering down the voltage on the VMID pin. Repeated enabling/disabling of the device
can cause audible pops at the output.
PD, Rev 4.2, July 2009
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
