Production Data
WM8325
ADDRESS
R16401
BIT
LABEL
ON_PIN_CINT
DESCRIPTION
ON pin interrupt.
12
(4011h)
(Rising and Falling Edge triggered)
Note: Cleared when a ‘1’ is written.
Interrupt Status
1
R16409
(4019h)
IM_ON_PIN_CINT
Interrupt mask.
12
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Table 6 ON Pin Interrupt
11.7 RESET PIN FUNCTION
The R¯¯E¯S¯E¯T¯ pin is an active low input/output which is used to command Hardware Resets in the
WM8325 and in other connected devices. The pin is an open-drain type, with integrated pull-up; it can
be driven low by external sources or by the WM8325 itself.
The WM8325 drives the R¯¯E¯S¯E¯T¯ pin low in the OFF state. The output status of the R¯¯E¯S¯E¯T¯ pin in
SLEEP is configurable; this is determined by the RST_SLPENA register bit as defined in Table 7.
The WM8325 clears the R¯¯E¯S¯E¯T¯ pin following the transition to ON. On completion of the state
transition, the R¯¯E¯S¯E¯T¯ pin is held low for a further delay time period, extending the R¯¯E¯S¯E¯T¯ low
duration. The R¯¯E¯S¯E¯T¯ delay period is set by the RST_DUR register bit. See Figure 6 for further
details.
The WM8325 detects a Hardware Reset request whenever the R¯¯E¯S¯E¯T¯ pin is driven low by an
external source. In this event, the WM8325 resets the internal control registers (excluding the RTC)
and initiates a start-up sequence. See Section 24.
It is possible to mask the R¯¯E¯S¯E¯T¯ pin input in the SLEEP state by setting the RST_SLP_MSK register
bit. In SLEEP mode, if RST_SLP_MSK is set, the WM8325 will take no action if the R¯¯E¯S¯E¯T¯ pin is
pulled low.
Note that the R¯¯E¯S¯E¯T¯ pin control registers are locked by the WM8325 User Key. These registers can
only be changed by writing the appropriate code to the Security register, as described in Section 12.4.
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R16390 (4006h)
Reset Control
RST_SLP_MSK
Masks the R¯¯E¯S¯E¯T¯ pin input in
SLEEP mode
5
1
0 = External R¯¯E¯S¯E¯T¯ active in SLEEP
1 = External R¯¯E¯S¯E¯T¯ masked in
SLEEP
Protected by user key
RST_SLPENA
RST_DUR
Sets the output status of R¯¯E¯S¯E¯T¯ pin
in SLEEP
4
1
0 = R¯¯E¯S¯E¯T¯ high (not asserted)
1 = R¯¯E¯S¯E¯T¯ low (asserted)
Protected by user key
Delay period for releasing R¯¯E¯S¯E¯T¯
after ON or WAKE sequence
1:0
11
00 = 3ms
01 = 11ms
10 = 51ms
11 = 101ms
Protected by user key
Table 7 RESET Pin Control Registers
The WM8325 can generate an Auxiliary Reset output via a GPIO pin configured as “Auxiliary Reset”
output (see Section 21). This signal is asserted in the OFF state. The status of the Auxiliary Reset in
the SLEEP state is configurable, using the AUXRST_SLPENA register bit as defined in Table 8.
PD, February 2012, Rev 4.0
39
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
