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WM8321GEFL/RV 参数 Datasheet PDF下载

WM8321GEFL/RV图片预览
型号: WM8321GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 253 页 / 1578 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8321  
13 CLOCKING AND OSCILLATOR CONTROL  
13.1 GENERAL DESCRIPTION  
The WM8321 incorporates a 32.768kHz crystal oscillator in order to maintain the Real Time Clock  
(RTC). An external crystal is normally required. Alternatively, a 32.768kHz signal may be input directly  
on the XTI pin. The crystal oscillator and RTC are enabled at all times, including the OFF and  
BACKUP power states. It is possible to disable the crystal oscillator in BACKUP for power-saving  
RTC ‘unclocked’ mode if desired. The WM8321 clock functions are illustrated in Figure 16.  
Figure 16 Clocking Configuration  
The 32.768kHz crystal oscillator is enabled using the XTAL_ENA register. The crystal oscillator is  
enabled in the OFF, ON and SLEEP power states when XTAL_ENA = 1. The status of the crystal  
oscillator in BACKUP is selected using the XTAL_BKUPENA register.  
Note that the XTAL_ENA field is set via OTP/ICE settings only; it cannot be changed by writing to the  
control register. If the crystal is omitted, and an external 32.768kHz signal is connected as an input to  
the XTI pin, it is still required to set XTAL_ENA = 1 for normal operation.  
The crystal oscillator can be disabled in the BACKUP state by setting the XTAL_BKUPENA register  
bit to 0. This feature may be used to minimise the device power consumption in the BACKUP state,  
as described in Section 20.5. The crystal oscillator is maintained in the BACKUP state if both  
XTAL_ENA and XTAL_BKUPENA are set to 1.  
The CLKOUT signal, derived from the 32.768kHz oscillator, can be enabled or disabled directly by  
writing to the CLKOUT_ENA register in the ON or SLEEP power states. The CLKOUT can also be  
controlled as part of the power state transitions using the CLKOUT_SLOT and CLKOUT_SLP_SLOT  
register fields. See Section 11.3 for a description of the state transition timeslots.  
The CLKOUT pin may be configured as a CMOS output or as an Open-Drain output. The CLKOUT  
signal is referenced to the DBVDD power domain.  
The status of the crystal oscillator is indicated by the XTAL_OK register bit. If the crystal oscillator  
fails to start, or if it stops for any reason, then the XTAL_OK register will be set to 0.  
An internal RC oscillator is available in order to provide CLKOUT functionality during start-up of the  
crystal oscillator. This function is selectable using the XTAL_INH register bit, as described below.  
If XTAL_INH = 0, then the internal RC oscillator provides the CLKOUT signal in the event that the  
crystal oscillator has not fully started up prior to an ‘ON’ state transition event. A glitch-free transition  
between the clock sources is implemented after the crystal oscillator is ready.  
If XTAL_INH = 1, then an ‘ON’ state transition is delayed until the crystal oscillator has fully started  
up. This may be desirable if the CLKOUT signal is used as a clock for another circuit, to ensure that  
CLKOUT signal has been verified before the ‘ON’ state transition occurs. Note that the CLKOUT  
output is always disabled in the OFF power state; it is typically enabled as part of the ‘ON’ state  
transition sequence. Setting XTAL_INH = 1 ensures that the CLKOUT output cannot be enabled until  
the crystal frequency has been verified.  
If XTAL_INH = 1, and the crystal oscillator fails to start, then a System Reset will be scheduled after a  
timeout period of approximately 32 seconds. See Section 24 for details of System Resets.  
PD, February 2012, Rev 4.0  
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