WM8321
Production Data
Figure 2 Control Interface Timing - 4-wire (SPI) Control Mode (Write Cycle)
Figure 3 Control Interface Timing - 4-wire (SPI) Control Mode (Read Cycle)
Test Conditions
TJ = -40ºC to +125 ºC unless otherwise stated.
PARAMETER
SYMBOL
tCSU
tCHO
tSCY
MIN
40
10
200
80
80
40
10
0
TYP
MAX
UNIT
ns
C¯¯S falling edge to SCLK1 rising edge
SCLK1 falling edge to C¯¯S rising edge
SCLK1 pulse cycle time
ns
ns
SCLK1 pulse width low
tSCL
ns
SCLK1 pulse width high
tSCH
tDSU
tDHO
tps
ns
SDA1 to SCLK1 set-up time
SDA1 to SCLK1 hold time
ns
ns
Pulse width of spikes that will be suppressed
SCLK1 falling edge to SDOUT1 transition
5
ns
tDL
40
ns
The C¯¯S pin must be held high for at least 1s after every register write operation in SPI mode.
PD, February 2012, Rev 4.0
28
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
