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WM8321GEFL/RV 参数 Datasheet PDF下载

WM8321GEFL/RV图片预览
型号: WM8321GEFL/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 处理器电源管理子系统 [Processor Power Management Subsystem]
分类和应用:
文件页数/大小: 253 页 / 1578 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data  
WM8321  
Note that a transition from the SLEEP state to the OFF state is not a controlled transition. If an ‘OFF’  
event occurs whilst in the SLEEP state, then the WM8321 will select the OFF state, but all the  
enabled converters and regulators will be disabled immediately; the time-controlled sequence is not  
implemented in this case. See Section 11.3 for details of the WM8321 ‘OFF’ events.  
The current power state of the WM8321 can be read from the MAIN_STATE register field. A restricted  
definition of this field is shown in Table 1. Note that other values of MAIN_STATE are defined for  
transition states, but it is recommended that only the values quoted below should be used to confirm  
power state transitions.  
A power state transition to the BACKUP, SLEEP, ON or OFF state is indicated by the Interrupt bits  
described in Section 11.4.  
ADDRESS  
BIT  
LABEL  
DEFAULT  
DESCRIPTION  
Main State Machine condition  
0_0000 = OFF  
R16397  
(400Dh)  
MAIN_STATE [4:0]  
4:0  
0_0000  
System  
Status  
0_1011 = PROGRAM  
1_1100 = SLEEP  
1_1111 = ACTIVE (ON)  
Table 1 Power State Readback  
11.3 POWER STATE CONTROL  
The OFF, ON, SLEEP and WAKE sequences are initiated by many different conditions. When such a  
condition occurs, the WM8321 schedules a series of 5 timeslots, enabling a sequence of  
enable/disable events to be controlled. The nominal duration of the timeslots is fixed at 2ms, though  
this may be extended if any selected circuit has not started up within this time, as described later in  
this section. The OFF, SLEEP and WAKE sequences commence after a programmable delay set by  
PWRSTATE_DLY. This allows a host processor to request a WM8321 state transition and then  
complete other tasks before the transition actually occurs.  
The ON sequence is the transition from OFF to ON power states. Each LDO and each DC-DC  
Converter may be associated with any one of the available timeslots in the ON sequence. This  
determines the time, within the sequence, at which that DC-DC Converter or LDO will be enabled  
following an ‘ON’ event.  
The clock output (CLKOUT) and GPIO pins configured as External Power Enable (EPE) outputs can  
also be associated with any one of the available timeslots in the ON sequence. The EPE function is a  
logic output that may be used to control external circuits, including external DC-DC converters.  
An example ‘ON’ state transition sequence is illustrated in Figure 5. Each of the DC-DC Converters  
and LDO regulators can be individually assigned to one of the five timeslots (shown as T1, T2, T3,  
T4, T5), providing total flexibility in the power sequence.  
Figure 5 Example Control Sequence for ‘ON’ State Transition  
PD, February 2012, Rev 4.0  
31  
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