Production Data
WM8321
33 REVISION HISTORY
DATE
REV
DESCRIPTION OF CHANGES
CHANGED
BY
October 2010
2.0
2.0
SDOUT1 description amended to Open Drain, with external pull-up required.
PH
PH
Default value of PWRSTATE_DLY corrected.
December
2010
Undervoltage margin specified for all DC-DC converters.
Overvoltage margin specified for DC-DC converters 1,2.
Chip Temperature (AUX_DATA) equation updated.
Added notes that SLEEP > OFF is not a controlled transition; converters and
regulators are disabled immediately.
07/03/11
2.0
PH
RESET pin description updated to note integrated pull-up.
IRQ description updated to note pull-up in Open Drain mode.
System Reset and Device Reset descriptions updated, consistent with the
Summary Table.
Recommended external pull-up resistances added in Pin Description.
Internal pull-up / pull-down resistances added in Electrical Characteristics.
Noted Active High (non-inverted) polarity for GPIO “Power On/Off request”
function is not fully supported in development mode.
Noted maximum limit on Software Resets. Also clarification of the maximum
number of Watchdog / Undervoltage Device Resets.
25/03/11
3.0
PH
Correction to DBVDD test conditions (Section 7.7).
RTC_PINT_FREQ definition updated.
DC-DC output inductor saturation limit recommendations added.
SYSOK_THR register description updated.
Quiescent current characteristics updated for DC-DC 1-4.
Backup battery power updated; Charger control registers deleted.
LDO11 output amended for LDO11_VSEL_SRC=1 and DC-DC1 disabled.
OTP Register Map overview correction (GPn_TRI replaced with GPn_ENA).
LDO11 maximum output current increased (only for PVDD ≥ 3.1V).
Electrical Characteristics updated.
15/09/11
4.0
PH
01/02/12
14/02/12
4.0
4.0
PH
DC3_STNBY_LIM, DC4_STNBY_LIM descriptions updated.
SYSOK_THR description updated.
Product status updated to Production Data
JMacD
PD, February 2012, Rev 4.0
253
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
