Production Data
WM8321
29 REGISTER BITS BY ADDRESS
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R0 (00h)
Reset ID
CHIP_ID [15:0]
Writing to this register causes a Software Reset. The
register map contents may be reset, depending on
SW_RESET_CFG.
15:0
0000_0000
_0000_000
0
Reading from this register will indicate Chip ID.
Register 00h Reset ID
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R1 (01h)
Revision
PARENT_REV
[7:0]
The revision number of the parent die
15:8
7:0
0000_0000
0000_0000
CHILD_REV
[7:0]
The revision number of the child die (when present)
Register 01h Revision
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R16384
(4000h)
Parent ID
PARENT_ID
[15:0]
The ID of the parent die
15:0
0110_0010
_0100_011
0
Register 4000h Parent ID
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
REFER TO
R16385
(4001h)
PVDD
SYSLO_ERR_
ACT [1:0]
SYSLO Error Action
15:14
00
Selects the action taken when SYSLO is asserted
00 = Interrupt
Control
01 = WAKE transition
10 = Reserved
11 = OFF transition
11
SYSLO_STS
0
SYSLO Status
0 = Normal
1 = PVDD is below SYSLO threshold
SYSLO threshold (falling PVDD)
SYSLO_THR
[2:0]
6:4
010
This is the falling PVDD voltage at which SYSLO will be
asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
SYSOK_THR
[2:0]
SYSOK threshold (rising PVDD)
2:0
101
This is the rising PVDD voltage at which SYSOK will be
asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is added to
these threshold levels.
Register 4001h PVDD Control
PD, February 2012, Rev 4.0
145
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
