Production Data
WM8321
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
WDOG_SECA
CT
Secondary action of Watchdog timeout
(taken after 2 timeout periods)
9:8
10
00 = No action
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by user key
Primary action of Watchdog timeout
00 = No action
WDOG_PRIMA
CT
5:4
2:0
01
01 = Interrupt
10 = Device Reset
11 = WAKE transition
Protected by user key
Watchdog timeout period
000 = 0.256s
WDOG_TO
[2:0]
111
001 = 0.512s
010 = 1.024s
011 = 2.048s
100 = 4.096s
101 = 8.192s
110 = 16.384s
111 = 32.768s
Protected by user key
Table 79 Controlling the Watchdog Timer
The Watchdog timeout interrupt event is indicated by the WDOG_TO_EINT register field. This
secondary interrupt triggers a primary Watchdog Interrupt, WDOG_INT (see Section 23). This can be
masked by setting the mask bit as described in Table 80.
ADDRESS
R16401
(4011h)
BIT
LABEL
DESCRIPTION
Watchdog timeout interrupt.
(Rising Edge triggered)
WDOG_TO_EINT
11
Interrupt Status
1
Note: Cleared when a ‘1’ is written.
R16409
(4019h)
IM_WDOG_TO_EINT
Interrupt mask.
11
0 = Do not mask interrupt.
1 = Mask interrupt.
Interrupt Status
1 Mask
Default value is 1 (masked)
Table 80 Watchdog Timer Interrupts
PD, February 2012, Rev 4.0
135
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
