Production Data
WM8321
The WM8321 can also indicate the status of the SYSOK signal via a GPIO pin configured as a “PVDD
Good” output (see Section 21). A GPIO pin configured as “PVDD Good” output will be asserted when
the PVDD is above the SYSOK threshold.
Figure 27 PVDD Monitoring
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
SYSLO Error Action
R16385
(4001h)
SYSLO_ERR_
ACT
15:14
00
Selects the action taken when SYSLO is
asserted
PVDD
Control
00 = Interrupt
01 = WAKE transition
10 = Reserved
11 = OFF transition
SYSLO Status
SYSLO_STS
11
0
0 = Normal
1 = PVDD is below SYSLO threshold
SYSLO threshold (falling PVDD)
SYSLO_THR
[2:0]
6:4
010
This is the falling PVDD voltage at which
SYSLO will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
SYSOK_THR
[2:0]
SYSOK threshold (rising PVDD)
2:0
101
This is the rising PVDD voltage at which
SYSOK will be asserted
000 = 2.8V
001 = 2.9V
…
111 = 3.5V
Note that the SYSOK hysteresis margin is
added to these threshold levels.
Table 78 PVDD Monitoring Control
PD, February 2012, Rev 4.0
133
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
