WM8253
Production Data
3
2.5
2
9
8
7
6
5
4
3
2
1
1.5
1
0.5
0
0
0
0
64
128
192
256
64
128
192
256
Gain register value (PGA[7:0])
Gain register value (PGA[7:0])
Figure 7 PGA Gain Characteristic
Figure 8 Peak Input Voltage to Match ADC Full-scale Range
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA should be offset to match the full-scale range of the ADC (VFS = 2.0V). For
negative-going input video signals, a black level (zero differential) output from the PGA should be
offset to the top of the ADC range by setting register bits PGAFS[1:0]=10. For positive going input
signal the black level should be offset to the bottom of the ADC range by setting PGAFS[1:0]=11.
Bipolar input video is accommodated by setting PGAFS[1:0]=00 or PGAFS[1:0]=01 (zero differential
input voltage gives mid-range ADC output).
OVERALL SIGNAL FLOW SUMMARY
Figure 9 represents the processing of the video signal through the WM8253.
OUTPUT
INVERT
BLOCK
INPUT
SAMPLING
BLOCK
OFFSET DAC PGA
ADC BLOCK
BLOCK
BLOCK
D2
x (65535/VFS
)
V1
V2
V3
D1
+0
if PGAFS[1:0]=11
X
+65535 if PGAFS[1:0]=10
+32767 if PGAFS[1:0]=0x
OP[3:0]
+
+
VIN
digital
analog
+
-
CDS = 1
CDS = 0
D2 = D1 if INVOP = 0
D2 =65535-D1 if INVOP = 1
VRESET
PGA gain
A = 0.78+(PGA[7:0]*7.57)/255
VVRLC
Offset
DAC
260mV*(DAC[7:0]-127.5)/127.5
VIN is VINP voltage sampled on video sample
VRLCEXT=1
VRLCEXT=0
VRESET is VINP sampled during reset clamp
VVRLC is voltage applied to VRLC pin
CDS, VRLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
RLC
DAC
VRLCSTEP*RLCV[3:0] + VRLCBOT
Figure 9 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC, optionally
set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
PD, Rev 4.1, August 2011
13
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
