WM8253
Production Data
MCLK VSMP
TIMING CONTROL
RS
FROM CONTROL
INTERFACE
CL
VS
CIN
S/H
+
-
TO OFFSET DAC
+
VINP
2
S/H
1
INPUT SAMPLING
BLOCK
RLC
CDS
EXTERNAL VRLC
CDS
VRLC/
VBIAS
4-BIT
RLC DAC
FROM CONTROL
INTERFACE
VRLCEXT
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
PD, Rev 4.1, August 2011
11
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
