WM8253
Production Data
OPERATING MODE TIMING DIAGRAMS
The following diagrams show 4-bit multiplexed output data and MCLK, VSMP and input video
requirements for operation of the most commonly used modes as shown in Table 3. The diagrams are
identical for both CDS and non-CDS operation.
Note that for extended Mode 4 operation (MCLK:VSMP ratios of 2n:1 where n 4) the latency is
given by:
Latency (in MCLK periods) = 16.5 + ( n – 4 ) * 2
16.5 MCLK PERIODS
MCLK
VSMP
VINP
OP[3:0]
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C D
(DEL = 00)
OP[3:0]
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
D
(DEL = 01)
OP[3:0]
(DEL = 10)
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B C
D
B
OP[3:0]
A
B C
A
B
C
D
A
B
C
D
A
B
C
D
A
C D
D
(DEL = 11)
Figure 14 Mode 1 Operation
24.5 MCLK PERIODS
MCLK
VSMP
VINP
SAMPLE
RESET
RS
RS
RS
RS
RS
RS
SAMPLE
VIDEO
VS
VS
VS
VS
VS
VS
OP[3:0]
(DEL = 00)
C
C
C
C
D
D
D
D
A B C
A B C
A B C
A B C
D
D
D
D
A B
A B
A B
A B
C
C
C
C
D
A B C
D
A B C
A B C
A B C
A B C
D
D
D
D
A B C
A B C
A B C
A B C
D
D
D
D
A B C D
A B C D
A B C D
A B C D
OP[3:0]
(DEL = 01)
D
D
D
A B C D D
OP[3:0]
(DEL = 10)
A B C
A B C
D
D
OP[3:0]
(DEL = 11)
Figure 15 Mode 2 Operation
PD, Rev 4.1, August 2011
19
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
