WM8253
Production Data
INPUT VIDEO SAMPLING
t
t
t
t
MCLKL
PER
MCLKH
VSMPH
MCLK
t
VSMPSU
VSMP
INPUT
t
t
t
t
RH
t
VPER
VH
VSU
RSU
VIDEO
Figure 1 Input Video Timing
Note:
1. See Page 15 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
MCLK period
tPER
27.7
ns
MCLK high period
MCLK low period
VSMP period
tMCLKH
tMCLKL
tVPER
tVSMPSU
tVSMPH
tVSU
13.85
13.85
300
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
VSMP set-up time
VSMP hold time
3
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
Notes:
10
tVH
3
tRSU
10
tRH
3
1.
2.
tVSU and tRSU denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
tPD
tPD
OP[3:0]
Figure 2 Output Data Timing
PD, Rev 4.1, August 2011
8
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
