WM8253
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25C, MCLK = 36MHz, mode 1 unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 16-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Max Gain
Min Gain
0.25
2.56
Vp-p
Vp-p
V
Input signal limits (see Note 2)
Full-scale transition error
VIN
0
AVDD
+60
Gain = 0dB;
PGA[7:0] = 07(hex)
-60
10
10
mV
Zero-scale transition error
Gain = 0dB;
-50
+50
mV
PGA[7:0] = 07(hex)
Differential non-linearity
Integral non-linearity
DNL
INL
2.4
17
12
LSB
LSB
Input referred noise
LSB rms
References
Upper reference voltage
Lower reference voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
VRT
VRB
VRTB
2.05
1.05
1.0
1
V
V
0.95
1.05
V
20
50
2
100
4.5
mA
1. 6
2
VRLC = 0 to AVDD
1
A
4
bits
V/step
V/step
V
RLCDAC step size
VRLCSTEP
VRLCBOT
VRLCTOP
RLCDACRNG = 0
RLCDACRNG = 1
RLCDACRNG = 0
RLCDACRNG = 1
RLCDACRNG = 0
RLCDACRNG = 1
0.18
0.123
0.3
RLCDAC output voltage at
code 0(hex)
0.2
V
RLCDAC output voltage at
code F(hex)
3.0
V
2.05
V
Offset DAC, Monotonicity Guaranteed
Resolution
8
bits
LSB
Differential non-linearity
Integral non-linearity
Step size
DNL
INL
0.2
0.6
LSB
2.03
-260
+260
mV/step
mV
Output voltage
Code 00(hex)
Code FF(hex)
mV
Notes:
1.
2.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC input range.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
PD, Rev 4.1, August 2011
6
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
