WM8216
Production Data
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, TA = 25°C, MCLK = 60MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
MIN
TYP
MAX
UNIT
CONDITIONS
Overall System Specification (including 10-bit ADC, PGA, Offset and CDS functions)
Conversion rate
60
MSPS
Vp-p
Vp-p
Vp-p
Vp-p
V
Full-scale input voltage range
(see Note 1)
LOWREFS=0, Max Gain
LOWREFS=0, Min Gain
LOWREFS=1, Max Gain
LOWREFS=1, Min Gain
0.25
3.03
0.15
1.82
Input signal limits (see Note 2)
Input capacitance
VIN
AGND-0.3
AVDD+0.3
10
45
20
pF
Input switching impedance
Full-scale transition error
Ω
mV
Gain = 0dB;
PGA[7:0] = 4B(hex)
Zero-scale transition error
Gain = 0dB;
20
mV
PGA[7:0] = 4B(hex)
Differential non-linearity
Integral non-linearity
DNL
INL
0.75
2
LSB
LSB
Channel to channel gain matching
Output noise
1%
0.2
2.15
%
Min Gain
Max Gain
LSB rms
LSB rms
References
Upper reference voltage
VRT
VRB
LOWREFS=0
LOWREFS=1
LOWREFS=0
LOWREFS=1
1.95
0.95
2.05
1.85
1.05
1.25
1.25
1.0
2.25
1.25
V
V
V
V
V
V
V
Ω
Lower reference voltage
Input return bias voltage
VRX
VRTB
Diff. reference voltage (VRT-VRB)
LOWREFS=0
LOWREFS=1
0.9
1.10
0.6
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
1
45
2
Ω
mA
Ω
VRLC output resistance
2
VRLC Hi-Z leakage current
RLCDAC resolution
VRLC = 0 to AVDD
1
µA
4
bits
V/step
V/step
V
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
VRLCSTEP
VRLCSTEP
VRLCBOT
AVDD=3.3V
LOWREFS = 0
AVDD=3.3V
0.173
0.11
0.4
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
VRLCTOP
VRLCTOP
LOWREFS = 0
AVDD=3.3V
0.4
3.0
V
V
V
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
LOWREFS = 0
2.05
code F(hex), RLCDACRNG = 1
RLCDAC
RLCDAC
Notes:
DNL
INL
-0.5
+0.5
LSB
LSB
+/-0.5
1.
Full-scale input voltage denotes the peak input signal amplitude that can be gained to match the ADC full-scale
input range.
2.
Input signal limits are the limits within which the full-scale input voltage signal must lie.
PD Rev 4.0 March 2007
6
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
