WM8216
Production Data
PIN DESCRIPTION
PIN
1
NAME
RSMP
MCLK
DGND
SEN
TYPE
DESCRIPTION
Digital input
Digital input
Supply
Reset sample pulse (when CDS=1) or clamp control (CDS=0)
Master (ADC) clock. This clock determines the ADC conversion rate.
Digital ground.
2
3
4
Digital input
Supply
Enables the serial interface when high.
Digital supply, all digital I/O pins.
Serial data input.
5
DVDD2
SDI
6
Digital input
Digital input
No connect
No connect
7
SCK
Serial clock.
8
NC
No internal connection.
9
NC
No internal connection.
Digital output data bus. ADC output data (d9:d0) is available in 10-bit parallel
format.
10
11
12
13
14
15
16
17
18
19
OP[0]
OP[1]
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d0 (LSB)
d1
OP[2]
d2
OP[3]
d3
OP[4]
d4
OP[5]
d5
OP[6]
d6
OP[7]
d7
OP[8]
d8
OP[9]/SDO
d9 (MSB)
Alternatively, pin OP[9]/SDO may be used to output register read-back data when
OEB=0, OPD(register bit)=0 and SEN has been pulsed high. See Serial Interface
description in Device Description section for further details.
20
21
22
AVDD
AGND1
VRB
Supply
Supply
Analogue supply. This must be operated at the same potential as DVDD1.
Analogue ground.
Analogue output Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Analogue output Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
23
24
25
VRT
VRX
VRLC/VBIAS
Analogue I/O
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
26
27
28
29
30
TEST
EINP
Analogue I/O
Analogue input
Analogue input
Supply
Used for test purposes only. Do not externally connect – leave this pin floating.
Even channel input video.
Odd channel input video.
Analogue ground.
OINP
AGND2
DVDD1
Supply
Digital supply for logic and clock generator. This must be operated at the same
potential as AVDD.
31
32
OEB
Digital input
Digital input
Output Hi-Z control. All digital outputs set to high-impedance state when input pin
OEB=1 or register bit OPD=1.
VSMP
Video sample pulse.
PD Rev 4.0 March 2007
4
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
